1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a layout of a metal-oxide-semiconductor (MOS) device.
2. Description of the Prior Art
A MOS transistor device is one of the most common semiconductor devices, and is usually applied for enlarging currents or signals in a circuit, as being an oscillator of a circuit, or as being a switch device of a circuit. Based on the development of semiconductor processes, the MOS transistors have been applied to high-power devices, in place of power bipolar transistors that have slower switching speeds and higher driving consumptions. Accordingly, vertical double-diffusion metal-oxide-semiconductor (VDMOS) devices and lateral-diffusion metal-oxide-semiconductor (LDMOS) devices have been introduced in recent years. It is an advantage of the VDMOS device that the usable area of its source region is larger. However, it is more difficult to integrate the manufacturing process of the VDMOS device with the current processes of integrated circuits. On the other hand, the advantage of the LDMOS device is that the process of fabricating the LDMOS device is simpler, and it is effortless to integrate the LDMOS device with the other integrated circuit devices because of its flatter structure.
Please refer to FIG. 1 through FIG. 3. FIG. 1 is a schematic diagram illustrating a layout of a prior art LDMOS device 50, FIG. 2 is a schematic cross-sectional diagram illustrating the LDMOS device 50 shown in FIG. 1 along a crossing line 6-6′, and FIG. 3 is a stereoscopic side-view diagram illustrating the LDMOS device 50 shown in FIG. 1. In order to clearly illustrate the structure and simplify the description, positions of field oxide layers are not shown in FIG. 1, and positions of plugs are not shown in FIG. 2 and FIG. 3.
As shown in FIG. 1 through FIG. 3, a prior art LDMOS device 50 includes a P-type semiconductor substrate 10, an N-type well 12 disposed in the semiconductor substrate 10, a first field oxide layer 14 disposed on part of the surface of the N-type well 12, a gate structure 16 covering part of the first field oxide layer 14, a P-body region 18 disposed in the semiconductor substrate 10 on one side of the first field oxide layer 14, a source region 20 disposed within the P-body region 18, an N-type drain region 22 disposed within the N-type well 12 on one side of the first field oxide layer 14, an N-type grade doped region 52 disposed within the N-type well 12 under the drain region 22, a butting contact plug 36, and a plurality of contact plugs 46.
The source region 20 includes an N-type source doped region 32 and a P-type source contact region 34 therein. The source doped region 32 is disposed between the gate structure 16 and the source contact region 34. Observing along a direction parallel with the gate structure 16, the source doped region 32 does not overlap the source contact region 34. The gate structure 16 includes a gate dielectric layer 28, a gate electrode 26 and a spacer structure 30. The butting contact plug 36 electrically connects the source doped region 32 with the source contact region 34, and the contact plugs 46 are electrically connected to the gate electrode 26.
The prior art LDMOS device 50 further includes a P+ guard ring 40, two second field oxide layers 42, a high-voltage P-well 48, and a plurality of contact plugs 44. The high-voltage P-well 48 is disposed in the semiconductor substrate 10, and surrounds the components, such as the gate structure 16, the drain region 22, the source region 20, and the P-body region 18. The P+ guard ring 40 is disposed on the surface of the semiconductor substrate 10, and above the high-voltage P-well 48. The components, such as the gate structure 16, the drain region 22, the source region 20, and the P-body region 18, are also surrounded by the P+ guard ring 40. One of the second field oxide layers 42 surrounds the P+ guard ring 40 from the inner side of the P+ guard ring 40, while the other second field oxide layer 42 surrounds the P+ guard ring 40 from the outer side of the P+ guard ring 40. The contact plugs 44 are electrically connected to the P+ guard ring 40 so as to control the voltage of the P+ guard ring 40.
When a voltage applied to the gate electrode 26 is greater than the threshold voltage, the prior art LDMOS transistor 50 will be turned on. In a normal condition, the signal inputted from the drain region 22 flows through the N-type well 12, and reaches the source region 20. In such a case, the N-type well 12 disposed under the first field oxide layer 14 and under the gate electrode 26 can be regarded as a resistor. When the high voltage signal passes through the resistor, it will be converted into an applicable low voltage signal.
While the semiconductor technology is developed into the deep-submicron process, the requirements for higher performance of MOS transistor devices, and for higher integration levels of components are expected. However, the dimension of the prior art LDMOS device cannot decrease unlimitedly. The sizes of the regions located in the LDMOS device, such as the size of the gate region, the size of the source region, the size of the drain region, the size of the N-type well and the size of the P-type doped region, must be maintained above their critical size, so that the LDMOS device is able to suffer a high voltage. As a result, layout of the LDMOS device has a huge length, and the LDMOS device therefore occupies a great deal of area in the integrated circuit. The integration level of the integrated circuit is then seriously affected. On the other hand, since a drain-source on-state resistance (also named Rdson for short) value of an LDMOS device is proportional to its device area, the Rdson value of the prior art LDMOS device cannot reduce unlimitedly either. In light of this, it is still a great challenge for the device designer to reduce the length and the Rdson of the LDMOS device.